1. Field of the Invention
The present invention relates to methods and systems for generating error correction codes (ECCs), more particularly to methods and apparatuses for an optical disc drive, which efficiently reduces data accessing time during ECC encoding.
2. Description of the Prior Art
Conventional processes for generating error correction codes during encoding involves pre-storing source data in a dynamic random access memory (DRAM). Data stored in the DRAM are usually addressed by the row address and column address, and the DRAM is an array of memory cells accessing according to the row and column addresses.
In order to reduce number of pins on the package, the row and column addresses are multiplexed to share the same address pins. The DRAM is composed of capacitors, and each capacitor stores logic 1 or logic 0 for each data bit by storing the electric charge or not. The row address is sampled from the address pins and latched into the row address decoder when the RAS (Row Address Strobe) signal falls. After the row address is latched, the address on the address pins is switched to the column address and is sampled and latched into the column address decoder when the CAS (Column Address Strobe) signal falls. The data stored in the DRAM corresponding to the latched addresses is output once the CAS signal is stabilized. A technique called “page-mode” allows faster sequential accessing of DRAM, in which a row of DRAM is accessed by only latching the row address once. In the page-mode access, the RAS signal is kept while a new column address is supplied at each falling period of the CAS signal for accessing data from a corresponding memory cell of the DRAM. This technique reduces the column access time and lowers power consumption. The operation of accessing data in the same row is much faster than the operation of accessing data in different rows. For example, in the case of operating a 32 Kb DRAM with 7 bits of row address and 7 bits of column address, the access time required for address change from row to row belonging to the same column is around 5 times the access time for address change from column to column belonging to the same row.
Methods for generating error correction codes, such as generating the parity outer codes (PO codes) of Reed-Solomon product code (RSPC) on a digital versatile disc (DVD), which requires accessing data stored in memory cells with different row addresses. As a result, extensive time is consumed in switching a current row address to a subsequent one for the error correction code generation.
FIG. 1 is a schematic diagram of an ECC block 10 for DVDs. The ECC block 10 includes three regions, which are composed of multiple one-byte elements Bi,j (i=0-207, j=0-181). Region 11, composed of elements Bi,j with i=0-191 and j=0-171, stores the scrambled source data, Region 12 composed of elements Bi,j with i=192-207 and j=0-171 stores the PO codes, and region 13 composed of elements Bi,j with i=0-207 and j=172-181 stores the parity inner codes (PI codes). The generation of PO code Bi,j with i=192-207 is described by the following remainder polynomial Rj(X) for each column j with j=0-171, in which Gpo(x) is the PO generation polynomial:
                                          R            j                    ⁡                      (            x            )                          =                                            ∑                              i                =                192                            207                        ⁢                                          B                                  i                  ,                  j                                            ⁢                              x                                  207                  -                  i                                                              =                                    (                                                ∑                                      i                    =                    0                                    191                                ⁢                                                      B                                          i                      ,                      j                                                        ⁢                                      x                                          191                      -                      i                                                                                  )                        ⁢                          x              16                        ⁢                                                  ⁢            mod            ⁢                                                  ⁢                                          G                po                            ⁡                              (                x                )                                                                        Equation        ⁢                                  ⁢                  (          1          )                    
FIG. 2 is a schematic diagram illustrating an arrangement of the ECC block data stored in a DRAM. Before encoding, a sequence of source data received from a host is scrambled and buffered into the DRAM according to a mapping between the row/column address of memory words and the byte index Bi,j of the ECC block as shown in FIG. 2.
The storage unit of the DRAM is a word containing two bytes, and the storing sequence of the scrambled source data is {B0,0, B0,1, . . . B0,171, B1,0, . . . }.
According to the storing sequence, the row addresses of the scrambled source data are frequently switched to generate the PO codes, as each PO column for PO encoding is non-continuous in the direction of memory row address. The encoding process in the PO encoding direction has a low efficiency since large bandwidth and long time are required.
FIG. 3 is a block diagram of an error correction code generator 30 including a first memory (DRAM) 31, a multiplexer 32, and an encoder 33. Source data are provided from the host and stored in the first memory 31 of the ECC generator 30. Each column of the source data (Bi,j for i=0˜191) is sequentially read out from the first memory 31 for generating the corresponding PO codes (Bi,j for i=192˜207), in which only one byte of each word read from the first memory 31 is used. The multiplexer 32 selects one of the two bytes in each word and passes it to the encoder 33 for encoding.
For reading one PO column from the DRAM as shown in FIG. 2, it takes 147 times of row-crossing access (reading an element by jumping from one row to another) and 45 times of non-row-crossing access (reading an element in the same row as the previous one), adding up to the total of 192 rows of source data. Based on the previous example, row-crossing access requires five clock cycles, and non-row-crossing access only requires one clock cycle. Therefore, the total number of clock cycles for reading one PO column is 147×5+45=780 clock cycles. The ECC block has a total of 172 PO columns (i=0-171), hence the total amount of time for reading the scrambled source data in order to generate the PO codes is 172×780=134, 160 clock cycles. The ratio of page-mode data access to total data access is only 45/(45+147)=23.4%, which is very inefficient.